Very Large Scale Integrated (VLSI) circuit design practices dictate that data input timing with respect to the sample clock be accurately predicted and/or measured. If the predicted or measured data delay approaches the sample clock period, the sample clock must be carefully tuned to achieve valid timing with respect to the data input. Such tuning methods are labor intensive. The coax or delay lines used to adjust delays add size and weight to finished products. Moreover, tuning can not be done until parts have been integrated at a high level. If predicted or measured data delay variations exceed the sample clock period (reduced by set-up and hold times, and margin), either the interface can not be realized or the interface must be re-designed by slowing down the data rate by 1/2 and doubling the number of data wires. This adds complexity, size, power and cost to the finished product.